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Espressif Systems /ESP32-S2 /I2C0 /FIFO_ST

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Interpret as FIFO_ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RXFIFO_START_ADDR 0RXFIFO_END_ADDR 0TXFIFO_START_ADDR 0TXFIFO_END_ADDR 0 (RX_UPDATE)RX_UPDATE 0 (TX_UPDATE)TX_UPDATE 0SLAVE_RW_POINT

Description

FIFO status register

Fields

RXFIFO_START_ADDR

This is the offset address of the last received data, as described in I2C_NONFIFO_RX_THRES.
RXFIFO_END_ADDR

This is the offset address of the last received data, as described in I2C_NONFIFO_RX_THRES. This value refreshes when an I2C_RXFIFO_UDF_INT or I2C_TRANS_COMPLETE_INT interrupt is generated.
TXFIFO_START_ADDR

This is the offset address of the first sent data, as described in I2C_NONFIFO_TX_THRES.
TXFIFO_END_ADDR

This is the offset address of the last sent data, as described in I2C_NONFIFO_TX_THRES.

The value refreshes when an I2C_TXFIFO_OVF_INT or I2C_TRANS_COMPLETE_INT interrupt is generated.
RX_UPDATE

Write 0 or 1 to I2C_RX_UPDATE to update the value of I2C_RXFIFO_END_ADDR and I2C_RXFIFO_START_ADDR.
TX_UPDATE

Write 0 or 1 to I2C_TX_UPDATE to update the value of I2C_TXFIFO_END_ADDR and I2C_TXFIFO_START_ADDR.
SLAVE_RW_POINT

The received data in I2C slave mode.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data